Two of the primary characteristics of a power metal-oxide semiconductor field effect transistor (MOSFET) are its breakdown voltage and on-resistance. It is typically desirable to design a MOSFET with a relatively high breakdown voltage such that it can withstand high voltage transients and operate within a greater safe operating area (SOA). At the same time, it is also desirable to design the MOSFET such that it has a low on-resistance, because on-resistance per unit area directly impacts die size and cost. Unfortunately, there is a fundamental trade-off between breakdown voltage and on-resistance.
Low voltage MOSFETS (e.g., those with voltages of less than approximately 15 V) commonly incorporate an active drift region since the gate oxide of such devices does not experience high stress. The on-resistance of these low-voltage active drift structures is fairly low. High voltage MOSFETs (e.g., those with voltages of greater than about 15 V), on the other hand, often incorporate a field drift region (e.g., a shallow trench isolation, or “STI”) in order to reduce gate stress. The on-resistance of such structures is increased as there surface conduction (a low resistance path) is effectively removed.
Accordingly, there is a need for MOSFET structure that is capable of better optimizing the trade-off between breakdown voltage and on-resistance per unit area. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.